Manufactured semiconductor chips may have defects. Test inputs from a tester generated by an automatic test pattern generator (ATPG) are applied to an integrated circuit to identify faulty circuit behaviors caused by a defect from a correct circuit behavior in the integrated circuit under test (CUT). Power defects in the power circuit of the integrated circuit may have an effect of draining excessive power than normally required in a functional mode of the circuit. When such power defects exist, traditional diagnostic techniques are ineffective in isolating them and may lead to misleading conclusions. Therefore, when testing an integrated circuit, it is necessary to distinguish and correctly identify power defects from typical defects that are represented by stuck-at or transition faults.
Power defects are often identified by reapplying a verification test to the circuit under test (CUT) at different voltage settings. If the test passes at a high voltage, but fails at a low voltage, it is probable that the circuit design has a power defect. If this power defect is suspected to be related to a power drainage issue that exhibits different results depending on the applied voltage, power drainage from the CUT is monitored in a specialized power defect test and compared to the expected amount of power drainage to conclude whether or not the CUT satisfies the design criteria.
Testing each circuit with varying voltages for identifying power defects is impractical in a high volume manufacturing environment. Measuring power drainage during a power defect test often requires a more expensive and sophisticated measurement device on the tester. Furthermore, specific design knowledge about allowable power consumption and/or critical power issues is required to correctly identify the presence of power defects and resolve power design issues for real-life applications.
Benefits and solutions in a volume manufacturing environment for chip testing are provided where manufacturing yields are essential. Miscompare data is captured and stored for a power defect analysis. Instead of testing each chip for power measurement, the failure data is used to identify power defects, thus the time for power design testing is significantly reduced. As an added benefit, a sophisticated measurement device for power design testing can be eliminated for cost saving.